Complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing a circuit using an HDL, the designer describes the behavior of a system in terms of signals that are generated and propagated from one set of registers to another set of registers through various cells of combinatorial logic. HDLs provide a rich set of constructs to describe the functionality of each module. Cells may be combined and augmented to form even higher-level modules.
System-level integration may rely on reuse of previously created designs that have been provided either from within an enterprise or from a commercial provider. Libraries of pre-developed cells of logic have been developed that can be selected and included in a circuit design. Such logic blocks include, for example, adders, multipliers, filters, and other arithmetic and digital signal processing (DSP) functions from which system designs can be readily constructed. The logic blocks may further include memories and storage elements. The engineering community sometimes refers to these previously created cells as “IP (intellectual property) cells,” “cores,” or “IP cores,” and such terms may be used interchangeably herein.
The use of pre-developed IP cells permits faster design cycles by eliminating the redesign of circuits. Thus, using cells from a library may reduce design costs. Such pre-developed IP cells may be available for purchase by parties who desire the functionality provided by the core, but do not have the time and/or resources necessary to design them.
IP cells include a circuit design in the form of source code or a netlist that may be used in implementing the design in a programmable IC, such as a field programmable gate array (FPGA). IP Cells may be parameterizable. That is, the designer may specify values of parameters to tailor certain core functionality according to the designer's needs.
An IP cell may be integrated into a design by instantiating the code or netlist. The cell is then placed and routed along with the rest of the design to provide the desired functionality. Incorporation of an IP cell into a larger design, however, may not be a simple task. For example, different logic cores included in a design may be configured to communicate using different communication protocols, and each communication protocol may include a large number of configuration settings such as clock frequency, data width, etc. Moreover, additional logic may be required to be included to provide a communication interface between cells using incompatible communication protocols. Manual configurations of these settings and interface logic can be a time-consuming process.